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zilog worldwide headquarters ? 532 race street ? san jose, ca 95126-3432 telephone: 408.558.8500 ? fax: 408.558.8300 ? www.zilog.com product specification ps023803-0305 z8 gp tm microcontrollers zgp323h otp mcu family
disclaimer ps023803-0305 this publication is subject to replacement by a la ter edition. to determine whether a later edition exists, or to request copies of publications, contact: zilog worldwide headquarters 532 race street san jose, ca 95126-3432 telephone: 408.558.8500 fax: 408.558.8300 www. zilog .com zilog is a registered trademark of zilog inc. in the unit ed states and in other countri es. all other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. document disclaimer ?2005 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible us es and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not a ssume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. devi ces sold by zilog, inc. are covered by warranty and limitation of liability provisions a ppearing in the zilog, inc. terms and conditions of sale. zilog, inc. makes no warranty of merchantability or fitness for any purpose. e xcept with the express writt en approval of zilog, use of information, devices, or technology as critical components of life support syst ems is not authorized. no licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
zgp323h product specification ps023803-0305 revision history iii revision history each instance in table 1 reflects a change to this document from its previous revi- sion. to see more detail, click the appropriate link in the table. table 1. revision history of this document date revision level section description page # december 2004 02 changed low power consumption, stop and halt mode current values, deleted mask option note, clarified temperature ranges in tables 6 and 8 and 10. added new tables 9 and 10. also added characterization data to table 11 and changed program/erase endurance value in table 12. 1,2,10 11,12, 13,14, 15 removed preliminary designation all march 2005 03 minor change to table 9 electrical characteristics. added 20, 28 and 40- pin cdip parts in the ordering section. 11,90
zgp323h product specification ps023803-0305 table of contents iv table of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii development features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 xtal1 crystal 1 (time-based input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 xtal2 crystal 2 (time-based output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 port 0 (p07?p00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 port 1 (p17?p10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 port 2 (p27?p20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 port 3 (p37?p30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 reset (input, active low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 expanded register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 counter/timer functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 expanded register file control registers (0d) . . . . . . . . . . . . . . . . . . . . . . . . 66 expanded register file control registers (0f) . . . . . . . . . . . . . . . . . . . . . . . . . 71 standard control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
zgp323h product specification ps023803-0305 list of figures v list of figures figure 1. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. counter/timers diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. 20-pin pdip/soic/ssop/cdip* pin conf iguration . . . . . . . . . . . . . . 5 figure 4. 28-pin pdip/soic/ssop/cdip* pin conf iguration . . . . . . . . . . . . . . 6 figure 5. 40-pin pdip/cdip* pin configuration . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. 48-pin ssop pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. test load diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. port 0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. port 1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. port 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. port 3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13. port 3 counter/timer output configuration . . . . . . . . . . . . . . . . . . . 24 figure 14. program memory map (32k otp) . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 15. expanded register file architecture . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 16. register pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 17. register pointer?detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 18. glitch filter circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 19. transmit mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 20. 8-bit counter/timer circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 21. t8_out in single-pass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 22. t8_out in modulo-n mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 23. demodulation mode count capture flowchart . . . . . . . . . . . . . . . . 44 figure 24. demodulation mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 25. 16-bit counter/timer circ uits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 26. t16_out in single-pass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 27. t16_out in modulo-n mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 28. ping-pong mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 29. output circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 30. interrupt block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 31. oscillator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 32. port configuration register (pcon) (write only) . . . . . . . . . . . . . . 55 figure 33. stop mode recovery register . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
zgp323h product specification ps023803-0305 list of figures vi figure 34. sclk circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 35. stop mode recovery source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 36. stop mode recovery register 2 ((0f)dh:d2?d4, d6 write only) . . 61 figure 37. watch-dog timer mode register (write only) . . . . . . . . . . . . . . . . . 62 figure 38. resets and wdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 39. tc8 control register ((0d)o0h: read/write except where noted) 66 figure 40. t8 and t16 common control functions ((0d)01h: read/write) . . . 67 figure 41. t16 control register ((0d) 2h: read/write except where noted) . 69 figure 42. t8/t16 control register (0d)03h: read/write (except where noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 43. voltage detection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 44. port configuration register (pcon)(0f)00h: write only) . . . . . . . . 72 figure 45. stop mode recovery register ((0f)0bh: d6?d0=write only, d7=read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 46. stop mode recovery register 2 ((0f)0dh:d2?d4, d6 write only) 74 figure 47. watch-dog timer register ((0f) 0fh: write only). . . . . . . . . . . . . . 75 figure 48. port 2 mode register (f6h: write only). . . . . . . . . . . . . . . . . . . . . . 75 figure 49. port 3 mode register (f7h: write only) . . . . . . . . . . . . . . . . . . . . . 76 figure 50. port 0 and 1 mode register (f8h: write only) . . . . . . . . . . . . . . . . 77 figure 51. interrupt priority register (f9h: write only) . . . . . . . . . . . . . . . . . . 78 figure 52. interrupt request register (fah: read/write) . . . . . . . . . . . . . . . . 79 figure 53. interrupt mask register (fbh: read/write) . . . . . . . . . . . . . . . . . . . 79 figure 54. flag register (fch: read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 55. register pointer (fdh: read/write) . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 56. stack pointer high (feh: read/write) . . . . . . . . . . . . . . . . . . . . . . 81 figure 57. stack pointer low (ffh: read/write) . . . . . . . . . . . . . . . . . . . . . . . 81 figure 58. 20-pin cdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 59. 20-pin pdip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 60. 20-pin soic package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 61. 20-pin ssop package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 62. 28-pin soic package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 63. 28-pin cdip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 64. 28-pin pdip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 65. 28-pin ssop package diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 66. 40-pin pdip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 67. 40-pin cdip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
zgp323h product specification ps023803-0305 list of figures vii figure 68. 48-pin ssop package design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
zgp323h product specification ps023803-0305 list of tables viii list of tables table 1. revision history of this document . . . . . . . . . . . . . . . . . . . . . . . . . . . iii table 2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 3. power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 4. 20-pin pdip/soic/ssop/cdip* pin identification . . . . . . . . . . . . . . 5 table 5. 28-pin pdip/soic/ssop/cdip* pin identification . . . . . . . . . . . . . . 6 table 6. 40- and 48-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 9. gp323hs dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 10. gp323he dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 11. gp323ha dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 12. eprom/otp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 13. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14. port 3 pin function summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15. ctr1(0d)01h t8 and t16 common functions . . . . . . . . . . . . . . . . 35 table 16. interrupt types, sources, and vectors . . . . . . . . . . . . . . . . . . . . . . 52 table 17. irq register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 18. smr2(f)0dh:stop mode recovery register 2* . . . . . . . . . . . . . . . 58 table 19. stop mode recovery source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 20. watch-dog timer time select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 21. eprom selectable options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
zgp323h product specification ps023803-0305 development features 1 development features table 2 lists the features of zilog ? ?s zgp323h members. ? low power consumption?18mw (typical) ? t = temperature s = standard 0 to +70c e = extended -40 to +105c a = automotive -40 to +125c ? three standby modes: ? stop? (typical 1.8 a ) ? halt? (typical 0.8ma) ? low voltage reset ? special architecture to automate both generation and reception of complex pulses or signals: ? one programmable 8-bit counter/timer with two capture registers and two load registers ? one programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair ? programmable input glitch filter for pulse reception ? six priority interrupts ? three external ? two assigned to counter/timers ? one low-voltage detection interrupt ? low voltage detection and high voltage detection flags ? programmable watch-dog timer/power-on reset (wdt/por) circuits ? two independent comparators with programmable interrupt polarity ? programmable eprom options ? port 0: 0?3 pull-up transistors ? port 0: 4?7 pull-up transistors table 2. features device otp (kb) ram (bytes) i/o lines voltage range zgp323h otp mcu family 4, 8, 16, 32 237 32, 24 or 16 2.0v?5.5v
zgp323h product specification ps023803-0305 general description 2 ? port 1: 0?3 pull-up transistors ? port 1: 4?7 pull-up transistors ? port 2: 0?7 pull-up transistors ? eprom protection ? wdt enabled at por general description the zgp323h is an otp-based member of the mcu family of infrared microcon- trollers. with 237b of general-purpose ram and up to 32kb of otp, zilog ? ?s cmos microcontrollers offer fast-executi ng, efficient use of memory, sophisti- cated interrupts, input/output bit manipulation capabilities, automated pulse gen- eration/reception, and internal key-scan pull-up transistors. the zgp323h architecture (figure 1) is based on zilog?s 8-bit microcontroller core with an expanded register file allowing access to register-mapped peripher- als, input/output (i/o) circuits, and powerful counter/timer circuitry. the z8 ? offers a flexible i/o scheme, an efficient register and address space structure, and a number of ancillary features that are us eful in many consumer, automotive, com- puter peripheral, and battery- operated hand-held applications. there are three basic address spaces available to support a wide range of config- urations: program memory, register file and expanded register file. the regis- ter file is composed of 256 bytes (b) of ram. it includes 4 i/o port registers, 16 control and status registers, and 236 general-purpose registers. the expanded register file consists of two a dditional register groups (f and d). to unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the z8 gp otp offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (see figure 2). also included are a large number of user- selectable modes and two on-board comp arators to process analog signals with separate reference voltages. all signals with an overline, ? ?, are active low. for example, b/w , in which word is active low, and b /w, in which byte is active low. power connections use the conventional descriptions listed in table 3. note:
zgp323h product specification ps023803-0305 general description 3 figure 1. functional block diagram table 3. power connections connection circuit device power v cc v dd ground gnd v ss z8? core port 2 port 0 p21 p22 p23 p24 p25 p26 p27 p20 i/o bit programmable p04 p05 p06 p07 p00 p01 p02 p03 i/o nibble programmable register file 256 x 8-bit register bus internal address bus internal data bus expanded register file expanded register bus z8 ? core counter/timer 8 8-bit counter/timer 16 16-bit v dd v ss xtal reset pref1/p30 p31 p32 p33 p34 p35 p36 p37 port 3 machine timing & instruction control power 4 4 otp up to 32k x 8 port 1 p14 p15 p16 p17 p10 p11 p12 p13 i/o byte programmable 8 watch-dog timer low voltage detection high voltage detection 2 comparators note: refer to the specific package for available pins. power-on reset
zgp323h product specification ps023803-0305 pin description 4 figure 2. counter/timers diagram pin description the pin configuration for the 20-pin pdip/soic/ssop is illustrated in figure 3 and described in table 4. the pin configuration for the 28-pin pdip/soic/ssop are depicted in figure 4 and described in t able 5. the pin configurations for the 40-pin pdip and 48-pin ssop versions ar e illustrated in figure 5, figure 6, and described in table 6. for customer engineering code developm ent, a uv eraseable windowed cerdip packaging is offered in 20-pin, 28-pin, and 40-pin configurations. zilog does not recommend nor guarantee these pa ckages for use in production. hi16 lo16 16-bit t16 tc16h tc16l hi8 lo8 and/or logic clock divider glitch filter edge detect circuit 8-bit t8 tc8h tc8l 8 8 16 8 input sclk 1 2 48 timer 16 timer 8/16 timer 8 8 8 8 8 8
zgp323h product specification ps023803-0305 pin description 5 figure 3. 20-pin pdip/soic/ssop/cdip* pin configuration table 4. 20-pin pdip/soic/sso p/cdip* pin id entification pin # symbol function direction 1?3 p25?p27 port 2, bits 5,6,7 input/output 4 p07 port 0, bit 7 input/output 5v dd power supply 6 xtal2 crystal oscillator clock output 7 xtal1 crystal oscillator clock input 8?10 p31?p33 port 3, bits 1,2,3 input 11,12 p34. p36 port 3, bits 4,6 output 13 p00/pref1/p30 port 0, bit 0/analog reference input port 3 bit 0 input/output for p00 input for pref1/p30 14 p01 port 0, bit 1 input/output 15 v ss ground 16?20 p20?p24 port 2, bits 0,1,2,3,4 input/output p25 p26 p27 p07 v dd xtal2 xtal1 p31 p32 p33 p24 p23 p22 p21 p20 v ss p01 p00/pref1/p30 p36 p34 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20-pin pdip soic ssop cdip*
zgp323h product specification ps023803-0305 pin description 6 figure 4. 28-pin pdip/soic/ssop/cdip* pin configuration table 5. 28-pin pdip/soic/sso p/cdip* pin id entification pin symbol direction description 1-3 p25-p27 input/output port 2, bits 5,6,7 4-7 p04-p07 input/output port 0, bits 4,5,6,7 8v dd power supply 9 xtal2 output crystal, oscillator clock 10 xtal1 input crystal, oscillator clock 11-13 p31-p33 input port 3, bits 1,2,3 14 p34 output port 3, bit 4 15 p35 output port 3, bit 5 16 p37 output port 3, bit 7 17 p36 output port 3, bit 6 18 pref1/p30 port 3 bit 0 input analog ref input; connect to v cc if not used input for pref1/p30 19-21 p00-p02 input/output port 0, bits 0,1,2 22 v ss ground 23 p03 input/output port 0, bit 3 24-28 p20-p24 input/output port 2, bits 0-4 p24 p23 p22 p21 p20 p03 v ss p02 p01 p00 pref1/p30 p36 p37 p35 p25 p26 p27 p04 p05 p06 p07 v dd xtal2 xtal1 p31 p32 p33 p34 1 28-pin pdip soic ssop 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cdip*
zgp323h product specification ps023803-0305 pin description 7 figure 5. 40-pin pdip/cdip* pin configuration *windowed cerdip. these units are intended to be used for engineering code development only. zilog does not recommend/guarantee this package for production use. nc p25 p26 p27 p04 p05 p06 p14 p15 p07 vdd p16 p17 xtal2 xtal1 p31 p32 p33 p34 nc nc p24 p23 p22 p21 p20 p03 p13 p12 vss p02 p11 p10 p01 p00 pref1/p30 p36 p37 p35 reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 39 28 27 26 25 24 23 22 21 40-pin pdip cdip* note:
zgp323h product specification ps023803-0305 pin description 8 figure 6. 48-pin ssop pin configuration table 6. 40- and 48-pin configuration 40-pin pdip # 48-pin ssop # symbol 26 31 p00 27 32 p01 30 35 p02 34 41 p03 55 p04 67 p05 78 p06 10 11 p07 28 33 p10 29 34 p11 32 39 p12 nc p25 p26 p27 p04 n/c p05 p06 p14 p15 p07 vdd vdd n/c p16 p17 xtal2 xtal1 p31 p32 p33 p34 nc vss nc nc p24 p23 p22 p21 p20 p03 p13 p12 vss vss n/c p02 p11 p10 p01 p00 n/c pref1/p30 p36 p37 p35 reset 48-pin ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
zgp323h product specification ps023803-0305 pin description 9 33 40 p13 89 p14 910p15 12 15 p16 13 16 p17 35 42 p20 36 43 p21 37 44 p22 38 45 p23 39 46 p24 22 p25 33 p26 44 p27 16 19 p31 17 20 p32 18 21 p33 19 22 p34 22 26 p35 24 28 p36 23 27 p37 20 23 nc 40 47 nc 11 nc 21 25 reset 15 18 xtal1 14 17 xtal2 11 12, 13 v dd 31 24, 37, 38 v ss 25 29 pref1/p30 48 nc 6nc 14 nc 30 nc 36 nc table 6. 40- and 48-pin configuration (continued) 40-pin pdip # 48-pin ssop # symbol
zgp323h product specification ps023803-0305 absolute maximum ratings 10 absolute maximum ratings stresses greater than those listed in table 8 might cause permanent damage to the device. this rating is a stress rating only. functional operation of the device at any condition above those indicated in the operational sections of these specifica- tions is not implied. exposure to abso lute maximum rating conditions for an extended period might af fect device reliability. standard test conditions the characteristics listed in this product specification apply for standard test con- ditions as noted. all voltages are referenced to gnd. positive current flows into the referenced pin (see figure 7). figure 7. test load diagram table 7. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias ?40 125 c 1 storage temperature ?65 +150 c voltage on any pin with respect to v ss ?0.3 7.0 v 2 voltage on v dd pin with respect to v ss ?0.3 7.0 v maximum current on input and/or inactive output pin ?5 +5 a maximum output current from active output pin ?25 +25 ma maximum current into v dd or out of v ss 75 ma notes: 1. see ordering information. 2. this voltage applies to all pins except the following: v dd , p32, p33 and reset . from output under test 150pf
zgp323h product specification ps023803-0305 dc characteristics 11 capacitance table 8 lists the capacitances. dc characteristics table 8. capacitance parameter maximum input capacitance 12pf output capacitance 12pf i/o capacitance 12pf note: t a = 25 c, v cc = gnd = 0 v, f = 1.0 mhz, unmeasured pins returned to gnd table 9. gp323hs dc characteristics t a =0c to +70c units conditions notes symbol parameter v cc min typ(7) max v cc supply voltage 2.0 5.5 v see note 5 5 v ch clock input high voltage 2.0-5.5 0.8 v cc v cc +0.3 v driven by external clock generator v cl clock input low voltage 2.0-5.5 v ss ?0.3 0.4 v driven by external clock generator v ih input high voltage 2.0-5.5 0.7 v cc v cc +0.3 v v il input low voltage 2.0-5.5 v ss ?0.3 0.2 v cc v v oh1 output high voltage 2.0-5.5 v cc ?0.4 v i oh = ?0.5ma v oh2 output high voltage (p36, p37, p00, p01) 2.0-5.5 v cc ?0.8 v i oh = ?7ma v ol1 output low voltage 2.0-5.5 0.4 v i ol = 4.0ma v ol2 output low voltage (p00, p01, p36, p37) 2.0-5.5 0.8 v i ol = 10ma v offset comparator input offset voltage 2.0-5.5 25 mv v ref comparator reference voltage 2.0-5.5 0 v cc 1.75 v i il input leakage 2.0-5.5 ?1 1 av in = 0v, v cc pull-ups disabled r pu pull-up resistance 2.0v 225 675 k ? v in = 0v; pullups selected by mask option 3.6v 75 275 k ? 5.0v 40 160 k ?
zgp323h product specification ps023803-0305 dc characteristics 12 i ol output leakage 2.0-5.5 ?1 1 av in = 0v, v cc i cc supply current 2.0v 3.6v 5.5v 1 5 10 3 10 15 ma ma ma at 8.0 mhz at 8.0 mhz at 8.0 mhz 1, 2 1, 2 1, 2 i cc1 standby current (halt mode) 2.0v 3.6v 5.5v 0.5 0.8 1.3 1.6 2.0 3.2 ma ma ma v in = 0v, clock at 8.0mhz v in = 0v, clock at 8.0mhz v in = 0v, clock at 8.0mhz 1, 2, 6 1, 2, 6 1, 2, 6 i cc2 standby current (stop mode) 2.0v 3.6v 5.5v 2.0v 3.6v 5.5v 1.6 1.8 1.9 5 8 15 8 10 12 20 30 45 a a a a a a v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt is running v in = 0 v, v cc wdt is running v in = 0 v, v cc wdt is running 3 3 3 3 3 3 i lv standby current (low voltage) 1.2 6 a measured at 1.3v 4 v bo v cc low voltage protection 1.9 2.0 v 8mhz maximum ext. clk freq. v lvd v cc low voltage detection 2.4 v v hvd vcc high voltage detection 2.7 v notes: 1. all outputs unloaded, inputs at rail. 2. cl1 = cl2 = 100 pf. 3. oscillator stopped. 4. oscillator stops when v cc falls below v bo limit. 5. it is strongly recommended to ad d a filter capacitor (minimum 0.1 f), physically close to vcc and v ss pins if operating voltage fluctuations are anticipated, such as those resulting from driving an infrared led. 6. comparator and timers are on. interrupt disabled. 7. typical values shown are at 25 degrees c. table 10. gp323he dc characteristics t a = -40c to +105c units conditions notes symbol parameter v cc min typ(7) max v cc supply voltage 2.0 5.5 v see note 5 5 v ch clock input high voltage 2.0-5.5 0.8 v cc v cc +0.3 v driven by external clock generator v cl clock input low voltage 2.0-5.5 v ss ?0.3 0.4 v driven by external clock generator v ih input high voltage 2.0-5.5 0.7 v cc v cc +0.3 v v il input low voltage 2.0-5.5 v ss ?0.3 0.2 v cc v v oh1 output high voltage 2.0-5.5 v cc ?0.4 v i oh = ?0.5ma table 9. gp323hs dc characteristics (continued) t a =0c to +70c units conditions notes symbol parameter v cc min typ(7) max
zgp323h product specification ps023803-0305 dc characteristics 13 v oh2 output high voltage (p36, p37, p00, p01) 2.0-5.5 v cc ?0.8 v i oh = ?7ma v ol1 output low voltage 2.0-5.5 0.4 v i ol = 4.0ma v ol2 output low voltage (p00, p01, p36, p37) 2.0-5.5 0.8 v i ol = 10ma v offset comparator input offset voltage 2.0-5.5 25 mv v ref comparator reference voltage 2.0-5.5 0 v dd -1.75 v i il input leakage 2.0-5.5 ?1 1 av in = 0v, v cc pull-ups disabled r pu pull-up resistance 2.0v 200.0 700.0 k ? v in = 0v; pullups selected by mask option 3.6v 50.0 300.0 k ? 5.0v 25.0 175.0 k ? i ol output leakage 2.0-5.5 ?1 1 av in = 0v, v cc i cc supply current 2.0v 3.6v 5.5v 1 5 10 3 10 15 ma ma ma at 8.0 mhz at 8.0 mhz at 8.0 mhz 1, 2 1, 2 1, 2 i cc1 standby current (halt mode) 2.0v 3.6v 5.5v 0.5 0.8 1.3 1.6 2.0 3.2 ma ma ma v in = 0v, clock at 8.0mhz v in = 0v, clock at 8.0mhz v in = 0v, clock at 8.0mhz 1, 2, 6 1, 2, 6 1, 2, 6 i cc2 standby current (stop mode) 2.0v 3.6v 5.5v 2.0v 3.6v 5.5v 1.6 1.8 1.9 5 8 15 12 15 18 30 40 60 a a a a a a v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt is running v in = 0 v, v cc wdt is running v in = 0 v, v cc wdt is running 3 3 3 3 3 3 i lv standby current (low voltage) 1.2 6 a measured at 1.3v 4 v bo v cc low voltage protection 1.9 2.15 v 8mhz maximum ext. clk freq. v lvd v cc low voltage detection 2.4 v v hvd vcc high voltage detection 2.7 v notes: 1. all outputs unloaded, inputs at rail. 2. cl1 = cl2 = 100 pf. 3. oscillator stopped. 4. oscillator stops when v cc falls below v bo limit. 5. it is strongly recommended to ad d a filter capacitor (minimum 0.1 f), physically close to vcc and v ss pins if operating voltage fluctuations are anticipated, such as those resulting from driving an infrared led. 6. comparator and timers are on. interrupt disabled. 7. typical values shown are at 25 degrees c. table 10. gp323he dc characteristics (continued) t a = -40c to +105c units conditions notes symbol parameter v cc min typ(7) max
zgp323h product specification ps023803-0305 dc characteristics 14 table 11. gp323ha dc characteristics t a = -40c to +125c units conditions notes symbol parameter v cc min typ(7) max v cc supply voltage 2.0 5.5 v see note 5 5 v ch clock input high voltage 2.0-5.5 0.8 v cc v cc +0.3 v driven by external clock generator v cl clock input low voltage 2.0-5.5 v ss ?0.3 0.4 v driven by external clock generator v ih input high voltage 2.0-5.5 0.7 v cc v cc +0.3 v v il input low voltage 2.0-5.5 v ss ?0.3 0.2 v cc v v oh1 output high voltage 2.0-5.5 v cc ?0.4 v i oh = ?0.5ma v oh2 output high voltage (p36, p37, p00, p01) 2.0-5.5 v cc ?0.8 v i oh = ?7ma v ol1 output low voltage 2.0-5.5 0.4 v i ol = 4.0ma v ol2 output low voltage (p00, p01, p36, p37) 2.0-5.5 0.8 v i ol = 10ma v offset comparator input offset voltage 2.0-5.5 25 mv v ref comparator reference voltage 2.0-5.5 0 v dd -1.75 v i il input leakage 2.0-5.5 ?1 1 av in = 0v, v cc pull-ups disabled r pu pull-up resistance 2.0v 200 700 k ? v in = 0v; pullups selected by mask option 3.6v 50 300 k ? 5.0v 25 175 k ? i ol output leakage 2.0-5.5 ?1 1 av in = 0v, v cc i cc supply current 2.0v 3.6v 5.5v 1 5 10 3 10 15 ma ma ma at 8.0 mhz at 8.0 mhz at 8.0 mhz 1, 2 1, 2 1, 2 i cc1 standby current (halt mode) 2.0v 3.6v 5.5v 0.5 0.8 1.3 1.6 2.0 3.2 ma ma ma v in = 0v, clock at 8.0mhz v in = 0v, clock at 8.0mhz v in = 0v, clock at 8.0mhz 1, 2, 6 1, 2, 6 1, 2, 6 i cc2 standby current (stop mode) 2.0v 3.6v 5.5v 2.0v 3.6v 5.5v 1.6 1.8 1.9 5 8 15 15 20 25 30 40 60 a a a a a a v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt is running v in = 0 v, v cc wdt is running v in = 0 v, v cc wdt is running 3 3 3 3 3 3 i lv standby current (low voltage) 1.2 6 a measured at 1.3v 4 v bo v cc low voltage protection 1.9 2.15 v 8mhz maximum ext. clk freq. v lvd v cc low voltage detection 2.4 v
zgp323h product specification ps023803-0305 dc characteristics 15 v hvd vcc high voltage detection 2.7 v notes: 1. all outputs unloaded, inputs at rail. 2. cl1 = cl2 = 100 pf. 3. oscillator stopped. 4. oscillator stops when v cc falls below v bo limit. 5. it is strongly recommended to ad d a filter capacitor (minimum 0.1 f), physically close to vcc and v ss pins if operating voltage fluctuations are anticipated, such as those resulting from driving an infrared led. 6. comparator and timers are on. interrupt disabled. 7. typical values shown are at 25 degrees c. table 12. eprom/otp characteristics symbol parameter min. typ. max. unit notes erase time 15 minutes 1,3 data retention @ use years 10 years 2 program/erase endurance 100 cycles 1 notes: 1. for windowed cerdip package only. 2. standard: 0c to 70c; extended: -40c to +105c; automotive : -40c to +125c. determined using the arrhenius model, which is an industry standard for estimating data retention of floating gate technologies: af = exp[(ea/k)*(1/tuse - 1/tstress)] where: ea is the intrinsic activation energy (ev; typ. 0.8) k is boltzman?s constant (8.67 x 10-5 ev/k) k = -273.16c tuse = use temperature in k tstress = stress temperature in k 3. at a stable uv lamp output of 20mw/cm 2 table 11. gp323ha dc characteristics (continued) t a = -40c to +125c units conditions notes symbol parameter v cc min typ(7) max
zgp323h product specification ps023803-0305 ac characteristics 16 ac characteristics figure 8 and table 13 describe the altern ating current (ac) characteristics. figure 8. ac timing diagram clock stop mode recovery source clock setup 1 22 3 3 t in 7 4 5 6 7 irq n 8 9 11 10
zgp323h product specification ps023803-0305 ac characteristics 17 table 13. ac characteristics t a =0c to +70c (s) ?40c to +105c (e) ?40c to +125c (a) 8.0mhz watch-dog timer mode register (d1, d0) no symbol parameter v cc minimum maximum units notes 1 tpc input clock period 2.0?5.5 121 dc ns 1 2 trc,tfc clock input rise and fall times 2.0?5.5 25 ns 1 3 twc input clock width 2.0?5.5 37 ns 1 4 twtinl timer input low width 2.0 5.5 100 70 ns 1 5 twtinh timer input high width 2.0?5.5 3tpc 1 6 tptin timer input period 2.0?5.5 8tpc 1 7 trtin,tftin timer input rise and fall timers 2.0?5.5 100 ns 1 8 twil interrupt request low time 2.0 5.5 100 70 ns 1, 2 9 twih interrupt request input high time 2.0?5.5 5tpc 1, 2 10 twsm stop-mode recovery width spec 2.0?5.5 12 5tpc ns 3 4 11 tost oscillator start-up time 2.0?5.5 5tpc 4 12 twdt watch-dog timer delay time 2.0?5.5 2.0?5.5 2.0?5.5 2.0?5.5 5 10 20 80 ms ms ms ms 0, 0 0, 1 1, 0 1, 1 13 t por power-on reset 2.0?5.5 2.5 10 ms notes: 1. timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. 2. interrupt request through port 3 (p33?p31). 3. smr ? d5 = 1. 4. smr ? d5 = 0.
zgp323h product specification ps023803-0305 pin functions 18 pin functions xtal1 crystal 1 (time-based input) this pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator input. additionally, an optional ex ternal single-phase clock can be coded to the on-chip oscillator input. xtal2 crystal 2 (time-based output) this pin connects a parallel-resonant crystal or ceramic resonant to the on-chip oscillator output. port 0 (p07?p00) port 0 is an 8-bit, bidirectional, cmos-c ompatible port. these eight i/o lines are configured under software control as a nibble i/o port. the output drivers are push-pull or open-drain controlled by bit d2 in the pcon register. if one or both nibbles are needed for i/o operation, they must be configured by writing to the port 0 mode register. after a hardware reset, port 0 is configured as an input port. an optional pull-up transistor is available as a mask option on all port 0 bits with nibble select. internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. the port 0 direction is reset to its default state following an smr. notes:
zgp323h product specification ps023803-0305 pin functions 19 figure 9. port 0 configuration port 1 (p17?p10) port 1 (see figure 10) port 1 can be configured for standard port input or output mode. after por, port 1 is configured as an input port. the output drivers are either push-pull or open-drain and are cont rolled by bit d1 in the pcon register. the port 1 direction is reset to its default state following an smr. otp programming option 4 4 z8 gp otp port 0 (i/o) pad in out i/o open-drain resistive transistor pull-up v cc note:
zgp323h product specification ps023803-0305 pin functions 20 figure 10. port 1 configuration port 2 (p27?p20) port 2 is an 8-bit, bidirectional, cmos-c ompatible i/o port (see figure 11). these eight i/o lines can be independently config ured under software control as inputs or outputs. port 2 is always available fo r i/o operation. a mask option is available to connect eight pull-up transistors on this port. bits programmed as outputs are globally programmed as either push-pull or open-drain. the por resets with the eight bits of port 2 configured as inputs. port 2 also has an 8-bit input or and and gate, which can be used to wake up the part. p20 can be programmed to ac cess the edge-detection circuitry in demodulation mode. otp programming option 8 z8 gp otp port 1 (i/o) pad in out oen open-drain resistive transistor pull-up v cc
zgp323h product specification ps023803-0305 pin functions 21 figure 11. port 2 configuration port 3 (p37?p30) port 3 is a 8-bit, cmos-compatible fixed i/o port (see figure 12). port 3 consists of four fixed input (p33?p30) and four fixed output (p37?p34), which can be con- figured under software control for interrupt and as output from the counter/timers. p30, p31, p32, and p33 are standard cmos inputs; p34, p35, p36, and p37 are push-pull outputs. otp programming option z8 gp otp port 2 (i/o) pad in out i/o open-drain resistive transistor pull-up v cc
zgp323h product specification ps023803-0305 pin functions 22 figure 12. port 3 configuration two on-board comparators process analog signals on p31 and p32, with refer- ence to the voltage on pref1 and p33. the analog function is enabled by program- ming the port 3 mode register (bit 1). p31 and p32 are programmable as rising, falling, or both edge triggered interrupts (irq register bits 6 and 7). pref1 and p33 are the comparator reference voltage inputs. access to the counter timer edge- detection circuit is through p31 or p20 (see ?t8 and t16 common functions? - z8 gp otp port 3 (i/o) p32 (an2) p31 (an1) pref1 from stop mode recovery source of smr p33 (ref2) irq2, p31 data latch pref1/p30 p31 p32 p33 p34 p35 p36 p37 d1 1 = analog 0 = digital r247 = p3m + - + irq0, p32 data latch irq1, p33 data latch comp 1 comp2 dig. an.
zgp323h product specification ps023803-0305 pin functions 23 ctr1(0d)01h? on page 35). other edge detect and irq modes are described in table 14. comparators are powered down by entering stop mode. for p31?p33 to be used in a stop mode recovery (smr) source, these inputs must be placed into digital mode. 2 port 3 also provides output for each of the counter/timers and the and/or logic (see figure 13). control is performed by pr ogramming bits d5?d4 of ctr1, bit 0 of ctr0, and bit 0 of ctr2. table 14. port 3 pin function summary pin i/o counter/timers comparator interrupt pref1/p30 in rf1 p31 in in an1 irq2 p32 in an2 irq0 p33 in rf2 irq1 p34 out t8 ao1 p35 out t16 p36 out t8/16 p37 out ao2 p20 i/o in note:
zgp323h product specification ps023803-0305 pin functions 24 figure 13. port 3 counter/timer output configuration pad p34 comp1 v dd mux pcon, d0 mu x ctr0, d0 p31 p30 (pref1) p34 data t8_out + pad p35 v dd mux ctr2, d0 out 35 t16_out pad p36 v dd mux ctr1, d6 out 36 t8/t16_out pad p37 v dd mux pcon, d0 p37 data - p31 p3m d1 comp2 p32 p33 + - p32 p3m d1
zgp323h product specification ps023803-0305 functional description 25 comparator inputs in analog mode, p31 and p32 have a comparator front end. the comparator refer- ence is supplied to p33 and pref1. in this mode, the p33 internal data latch and its corresponding irq1 are diverted to the sm r sources (excluding p31, p32, and p33) as indicated in figure 12 on page 22. in digital mode, p33 is used as d3 of the port 3 input register, which then generates irq1. comparators are powered down by entering stop mode. for p31?p33 to be used in a stop mode recovery source, these inputs must be placed into digital mode. comparator outputs these channels can be programmed to be output on p34 and p37 through the pcon register. reset (input, active low) reset initializes the mcu and is accomplished either through power-on, watch- dog timer, stop mode recovery, low-voltage detection, or external reset. during power-on reset and watch-dog timer reset, the internally generated reset drives the reset pin low for the por time. any devices driving the external reset line must be open-drain to avoid damage from a possible conflict during reset con- ditions. pull-up is provided internally. when the z8 gp asserts (low) the reset pin, the internal pull-up is disabled. the z8 gp does not assert the reset pin when under vbo. the external reset does not initiate an exit from stop mode. functional description this device incorporates special functions to enhance the z8 ? ? functionality in consumer and battery-operated applications. program memory this device addresses up to 32kb of otp memory. the first 12 bytes are reserved for interrupt vectors. these locations contain the six 16-bit vectors that correspond to the six available interrupts. ram this device features 256b of ram. see figure 14. note: note:
zgp323h product specification ps023803-0305 functional description 26 figure 14. program memory map (32k otp) expanded register file the register file has been expanded to al low for additional system control regis- ters and for mapping of additional peripher al devices into the register address area. the z8 ? register address space (r0 through r15) has been implemented as 16 banks, with 16 registers per bank. these register groups are known as the on-chip rom reset start address irq5 irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 12 11 10 9 8 7 6 5 4 3 2 1 0 32768 location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) not accessible
zgp323h product specification ps023803-0305 functional description 27 erf (expanded register file). bits 7?4 of register rp select the working register group. bits 3?0 of register rp select the expanded register file bank. an expanded register bank is also referred to as an expanded register group (see figure 15). note:
zgp323h product specification ps023803-0305 functional description 28 figure 15. expanded register file architecture uuuuuuu0 00000000 00000000 00000000 00 0f 7f f0 ff ff spl 00000000 uuuuuuuu 00000000 uuuuuuuu uuuuuuuu uuuuuuuu 11111111 00000000 11001111 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu fe sph fd rp fc flags fb imr fa irq f9 ipr f8 p01m f7 p3m f6 p2m f5 reserved f4 reserved f3 reserved f2 reserved f1 reserved f0 reserved d7 d6 d5 d4 d3 d2 d1 d0 uu001101 u01000u0 11111110 (f) 0f wdtmr (f) 0e reserved (f) 0d smr2 (f) 0c reserved (f) 0b smr (f) 0a reserved (f) 09 reserved (f) 08 reserved (f) 07 reserved (f) 06 reserved (f) 05 reserved (f) 04 reserved (f) 03 reserved (f) 02 reserved (f) 01 reserved (f) 00 pcon 76543210 expanded register bank pointer working register uuuuuuuu uuuuuuuu 00000000 (d) 0c lvd (d) 0b hi8 (d) 0a lo8 (d) 09 hi16 (d) 08 lo16 (d) 07 tc16h (d) 06 tc16l (d) 05 tc8h (d) 04 tc8l (d) 03 ctr3 (d) 02 ctr2 (d) 01 ctr1 (d) 00 ctr0 group pointer register file (bank 0)** 00011111 * * 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 u = unknown * is not reset with a stop-mode recovery ** all addresses are in hexadecimal is not reset with a stop-mode recovery, except bit 0 bit 5 is not reset with a stop-mode recovery bits 5,4,3,2 not reset with a stop-mode recovery bits 5 and 4 not reset with a stop-mode recovery bits 5,4,3,2,1 not reset with a stop-mode recovery expanded reg. bank 0/group (0) * (0) 03 p3 (0) 02 p2 (0) 01 p1 (0) 00 p0 0 u u u u * * * * * * * * * * * expanded reg. bank f/group 0** expanded reg. bank 0/group 15** register pointer z8 ? standard control registers expanded reg. bank d/group 0 r ese t c on diti on
zgp323h product specification ps023803-0305 functional description 29 the upper nibble of the register pointer (see figure 16) selects which working reg- ister group, of 16 bytes in the register file, is accessed out of the possible 256. the lower nibble selects the expanded register file bank and, in the case of the z8 gp family, banks 0, f, and d are implemented. a 0h in the lower nibble allows the nor- mal register file (bank 0) to be addressed. any other value from 1h to fh exchanges the lower 16 registers to an expanded register bank. figure 16. register pointer example: z8 gp: (see figure 15 on page 28) r253 rp = 00h r0 = port 0 r1 = port 1 r2 = port 2 r3 = port 3 but if: r253 rp = 0dh r0 = ctr0 r1 = ctr1 r2 = ctr2 r3 = reserved r253 rp d7 d6 d5 d4 d3 d2 d1 d0 expanded register file pointer working register pointer default setting after reset = 0000 0000
zgp323h product specification ps023803-0305 functional description 30 the counter/timers are mapped into erf group d. access is easily performed using the following: ld rp, #0dh ; select erf d for access to bank d ; (working register group 0) ld r0,#xx ; load ctr0 ld 1, #xx ; load ctr1 ld r1, 2 ; ctr2 ctr1 ld rp, #0dh ; select erf d for access to bank d ; (working register group 0) ld rp, #7dh ; select expanded register bank d and working ; register group 7 of bank 0 for access. ld 71h, 2 ; ctrl2 register 71h ld r1, 2 ; ctrl2 register 71h register file the register file (bank 0) consists of 4 i/o port registers, 237 general-purpose reg- isters, 16 control and status registers (r0?r3, r4?r239, and r240?r255, respectively), and two expanded registers groups in banks d (see table 15) and f. instructions can access registers dire ctly or indirectly through an 8-bit address field, thereby allowing a short, 4-bit regi ster address to use the register pointer (figure 17). in the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. the register pointer addresses the starting location of the active working register group. working register group e0?ef can only be accessed through working registers and indirect addressing modes. note:
zgp323h product specification ps023803-0305 functional description 31 figure 17. register pointer?detail stack the internal register file is used for the stack. an 8-bit stack pointer spl (r255) is used for the internal stack that resides in the general-purpose registers (r4? r239). sph (r254) can be used as a general-purpose register. r 7 r 6 r 5 r 4 r 3 r 2 r 1 r the upper nibble of the register file address provided by the register pointer specifies the active working-register group. specified working register group register group 1 register group 0 i/o ports r253 the lower nibble of the register file address provided by the instruction points to the specified register. * rp = 00: selects register bank 0, working register group 0 r15 to r0 r15 to r4 * r3 to r0 * ff f0 ef e0 df d0 40 3f 30 2f 20 1f 10 0f 00 register group 2
zgp323h product specification ps023803-0305 functional description 32 timers t8_capture_hi?hi8(d)0bh this register holds the captured data from the output of the 8-bit counter/timer0. typically, this register holds the number of counts when the input signal is 1. t8_capture_lo?l08(d)0ah this register holds the captured data from the output of the 8-bit counter/timer0. typically, this register holds the number of counts when the input signal is 0. t16_capture_hi?hi16(d)09h this register holds the captured data from the output of the 16-bit counter/ timer16. this register holds the ms-byte of the data. t16_capture_lo?l016(d)08h this register holds the captured data from the output of the 16-bit counter/ timer16. this register holds the ls-byte of the data. counter/timer2 ms-byte hold register?tc16h(d)07h field bit position description t8_capture_hi [7:0] r/w captured data - no effect field bit position description t8_capture_l0 [7:0] r/w captured data - no effect field bit position description t16_capture_hi [7:0] r/w captured data - no effect field bit position description t16_capture_lo [7:0] r/w captured data - no effect field bit position description t16_data_hi [7:0] r/w data
zgp323h product specification ps023803-0305 functional description 33 counter/timer2 ls-byte hold register?tc16l(d)06h counter/timer8 high hold register?tc8h(d)05h counter/timer8 low hold register?tc8l(d)04h ctr0 counter/timer8 control register?ctr0(d)00h table 15 lists and briefly describes the fields for this register. field bit position description t16_data_lo [7:0] r/w data field bit position description t8_level_hi [7:0] r/w data field bit position description t8_level_lo [7:0] r/w data table 15. ctr0(d)00h counter/timer8 control register field bit position value description t8_enable 7------- r/w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------- r/w 0* 1 modulo-n single pass time_out --5------ r/w 0** 1 0 1 no counter time-out counter time-out occurred no effect reset flag to 0 t8 _clock ---43--- r/w 0 0** 0 1 1 0 1 1 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0** 1 disable data ca pture interrupt enable data capture interrupt
zgp323h product specification ps023803-0305 functional description 34 t8 enable this field enables t8 when set (written) to 1. single/modulo-n when set to 0 (modulo-n), the counter rel oads the initial value when the terminal count is reached. when set to 1 (single- pass), the counter stops when the termi- nal count is reached. timeout this bit is set when t8 times out (terminal co unt reached). to reset this bit, write a 1 to its location. writing a 1 is the only way to reset the terminal count status condition. reset this bit before using/enabling the counter/timers. the first clock of t8 might not have complete clock width and can occur any time when enabled. take care when using the or or and commands to manipulate ctr0, bit 5 and ctr1, bits 0 and 1 (demodulation mode). these instructions use a read-m odify-write sequence in which the current status from the ctr0 and ctr1 registers is ored or anded with the designated value and then written back into the registers. t8 clock this bit defines the frequency of the input signal to t8. counter_int_mask ------1- r/w 0** 1 disable time-o ut interrupt enable time-out interrupt p34_out -------0 r/w 0* 1 p34 as port output t8 output on p34 note: * indicates the value upon power-on reset. * *indicates the value upon power-on reset. not reset with a stop mode recovery. table 15. ctr0(d)00h counter/timer8 control register (continued) field bit position value description caution: note:
zgp323h product specification ps023803-0305 functional description 35 capture_int_mask set this bit to allow an interrupt when data is captured into either lo8 or hi8 upon a positive or negative edge detection in demodulation mode. counter_int_mask set this bit to allow an interrupt when t8 has a timeout. p34_out this bit defines whether p34 is used as a normal output pin or the t8 output. t8 and t16 common functions?ctr1(0d)01h this register controls the functions in common with the t8 and t16. table 16 lists and briefly describes the fields for this register. table 16. ctr1(0d)01h t8 and t16 common functions field bit position value description mode 7------- r/w 0* transmit mode demodulation mode p36_out/ demodulator_input -6------ r/w 0* 1 0* 1 transmit mode port output t8/t16 output demodulation mode p31 p20 t8/t16_logic/ edge _detect --54---- r/w 00** 01 10 11 00** 01 10 11 transmit mode and or nor nand demodulation mode falling edge rising edge both edges reserved
zgp323h product specification ps023803-0305 functional description 36 mode if the result is 0, the counter/timers are in transmit mode; otherwise, they are in demodulation mode. p36_out/demodulator_input in transmit mode, this bit defines whet her p36 is used as a normal output pin or the combined output of t8 and t16. in demodulation mode, this bit defines whether the input signal to the counter/timers is from p20 or p31. if the input signal is from port 31, a capture event may also generate an irq2 interrupt. to prevent generating an irq2, either disable the irq2 interrupt by clearing its imr bit d2 or use p20 as the input. transmit_submode/ glitch_filter ----32-- r/w 00* 01 10 11 00* 01 10 11 transmit mode normal operation ping-pong mode t16_out = 0 t16_out = 1 demodulation mode no filter 4 sclk cycle 8 sclk cycle reserved initial_t8_out/ rising edge ------1- r/w r w 0* 1 0* 1 0 1 transmit mode t8_out is 0 initially t8_out is 1 initially demodulation mode no rising edge rising edge detected no effect reset flag to 0 initial_t16_out/ falling_edge -------0 r/w r w 0* 1 0* 1 0 1 transmit mode t16_out is 0 initially t16_out is 1 initially demodulation mode no falling edge falling edge detected no effect reset flag to 0 note: *default at power-on reset * default at power-on reset. not reset with stop mode recovery. table 16. ctr1(0d)01h t8 and t16 common functions (continued) field bit position value description
zgp323h product specification ps023803-0305 functional description 37 t8/t16_logic/edge _detect in transmit mode, this field defines how the outputs of t8 and t16 are com- bined (and, or, nor, nand). in demodulation mode, this field defines which edge should be detected by the edge detector. transmit_submode/glitch filter in transmit mode, this field defines whether t8 and t16 are in the ping-pong mode or in independent normal operation mode. setting this field to ?normal operation mode? terminates the ?pin g-pong mode? operation. when set to 10, t16 is immediately forced to a 0; a setting of 11 forces t16 to output a 1. in demodulation mode, this field defines t he width of the glitch that must be fil- tered out. initial_t8_out/rising_edge in transmit mode, if 0, the output of t8 is set to 0 when it starts to count. if 1, the output of t8 is set to 1 when it starts to count. when the counter is not enabled and this bit is set to 1 or 0, t8_out is set to the opposite state of this bit. this ensures that when the clock is enabled, a transition occurs to the initial state set by ctr1, d1. in demodulation mode, this bit is set to 1 when a rising edge is detected in the input signal. in order to reset the mode, a 1 should be written to this location. initial_t16 out/falling _edge in transmit mode, if it is 0, the output of t16 is set to 0 when it starts to count. if it is 1, the output of t16 is set to 1 when it starts to count. this bit is effective only in normal or ping-pong mode (ctr1, d3; d2). when the counter is not enabled and this bit is set, t16_out is set to the opposite state of this bit. this ensures that when the clock is enabled, a transition occurs to the initial state set by ctr1, d0. in demodulation mode, this bit is set to 1 when a falling edge is detected in the input signal. in order to reset it, a 1 should be written to this location. modifying ctr1 (d1 or d0) while the counters are enabled causes unpredictable output from t8/16_out. ctr2 counter/timer 16 control register?ctr2(d)02h table 17 lists and briefly describes the fields for this register. note:
zgp323h product specification ps023803-0305 functional description 38 t16_enable this field enables t16 when set to 1. single/modulo-n in transmit mode, when set to 0, the counter reloads the initial value when it reaches the terminal count. when set to 1, the counter stops when the terminal count is reached. table 17. ctr2(d)02h: counter/timer16 control register field bit position value description t16_enable 7------- r w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------ r/w 0* 1 0 1 transmit mode modulo-n single pass demodulation mode t16 recognizes edge t16 does not recognize edge time_out --5----- r w 0* 1 0 1 no counter timeout counter timeout occurred no effect reset flag to 0 t16 _clock ---43--- r/w 00** 01 10 11 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0** 1 disable data capture int. enable data capture int. counter_int_mask ------1- r/w 0* disable timeout int. enable timeout int. p35_out -------0 r/w 0* 1 p35 as port output t16 output on p35 note: *indicates the value upon power-on reset. ** indicates the value upon power-on reset. not reset with a stop mode recovery.
zgp323h product specification ps023803-0305 functional description 39 in demodulation mode, when set to 0, t16 captures and reloads on detection of all the edges. when set to 1, t16 capt ures and detects on the first edge but ignores the subsequent edges. for details , see the description of t16 demodula- tion mode on page 47. time_out this bit is set when t16 times out (terminal count reached). to reset the bit, write a 1 to this location. t16_clock this bit defines the frequency of the input signal to counter/timer16. capture_int_mask this bit is set to allow an interrupt when data is captured into lo16 and hi16. counter_int_mask set this bit to allow an interrupt when t16 times out. p35_out this bit defines whether p35 is used as a normal output pin or t16 output. ctr3 t8/t16 control register?ctr3(d)03h table 18 lists and briefly describes the fields for this register. this register allows the t 8 and t 16 counters to be synchronized. table 18. ctr3 (d)03h: t8/t16 control register field bit position value description t 16 enable 7------- r r w w 0* 1 0 1 counter disabled counter enabled stop counter enable counter t 8 enable -6------ r r w w 0* 1 0 1 counter disabled counter enabled stop counter enable counter sync mode --5----- r/w 0** 1 disable sync mode enable sync mode
zgp323h product specification ps023803-0305 functional description 40 counter/timer functional blocks input circuit the edge detector monitors the input signal on p31 or p20. based on ctr1 d5? d4, a pulse is generated at the pos edge or neg edge line when an edge is detected. glitches in the input signal t hat have a width less than specified (ctr1 d3, d2) are filtered out (see figure 18). figure 18. glitch filter circuitry t8 transmit mode before t8 is enabled, the output of t8 depends on ctr1, d1. if it is 0, t8_out is 1; if it is 1, t8_out is 0. see figure 19. reserved ---43210 r w 1 x always reads 11111 no effect *indicates the value upon power-on reset. ** indicates the value upon power-on reset. not reset with a stop mode recovery. table 18. ctr3 (d)03h: t8/t16 control register (continued) field bit position value description mux glitch filter edge detector p31 p20 pos edge neg edge ctr1 d5,d4 ctr1 d6 ctr1 d3, d2
zgp323h product specification ps023803-0305 functional description 41 figure 19. transmit mode flowchart set timeout status bit (ctr0 d5) and generate timeout_int if enabled set timeout status bit (ctr0 d5) and generate timeout_int if enabled t8 (8-bit) transmit mode no t8_enable bit set ctr0, d7 yes ctr1, d1 value reset t8_enable bit 0 1 load tc8l reset t8_out load tc8h set t8_out enable t8 no t8_timeout yes single pass single modulo-n t8_out value 0 enable t8 no t8_timeout ye s pass? load tc8h set t8_out load tc8l reset t8_out 1
zgp323h product specification ps023803-0305 functional description 42 when t8 is enabled, the output t8_out switches to the initial value (ctr1, d1). if the initial value (ctr1, d1) is 0, tc8l is loaded; otherwise, tc8h is loaded into the counter. in single-pass mode (ctr0, d6), t8 counts down to 0 and stops, t8_out toggles, the timeout status bit (ctr0, d5) is set, and a timeout interrupt can be generated if it is enabled (ctr0, d1). in modulo-n mode, upon reaching terminal count, t8_out is toggled, but no interrupt is generated. from that point, t8 loads a new count (if the t8_out level now is 0), tc8l is loaded; if it is 1, tc8h is loaded. t8 counts down to 0, toggles t8_out, and sets the timeout sta- tus bit (ctr0, d5), thereby generating an interrupt if enabled (ctr0, d1). one cycle is thus completed. t8 then loads from tc8h or tc8l according to the t8_out level and repeats the cycle. see figure 20. figure 20. 8-bit counter/timer circuits you can modify the values in tc8h or tc8l at any time. the new values take effect when they are loaded. to ensure known operation do not write these registers at the time the values are to be loaded into the counter/timer. an initial count of 1 is not a llowed (a non-function occurs). an initial count of 0 causes tc8 to count from 0 to ffh to feh . ctr0 d1 negative edge positive edge z8 ? data bus irq4 ctr0 d2 sclk z8 ? data bus ctr0 d4, d3 clock t8_out lo8 tc8h tc8l clock select 8-bit counter t8 hi8 caution:
zgp323h product specification ps023803-0305 functional description 43 the letter h denotes hexadecimal values. transition from 0 to ffh is not a timeout condition. using the same instructions for stopping the counter/timers and setting the status bits is not recommended. two successive commands are necessary. first, the counter/timers must be stopped. second, the status bits must be reset. these commands are required because it takes one counter/timer clock interv al for the initiated event to actually occur. see figure 21 and figure 22. figure 21. t8_out in single-pass mode figure 22. t8_out in modulo-n mode t8 demodulation mode the user must program tc8l and tc8h to ffh . after t8 is enabled, when the first edge (rising, falling, or both depending on ctr1, d5; d4) is detected, it starts to count down. when a subsequent edge (rising, falling, or both depending on ctr1, d5; d4) is detected during counting, the current value of t8 is comple- mented and put into one of the capture registers. if it is a positive edge, data is put n ote: caution: tc8h counts counter enable command; t8_out switches to its initial value (ctr1 d1) t8_out toggles; timeout interrupt counter enable command; t8_out switches to its initial value (ctr1 d1) timeout interrupt timeout interrupt t8_out t8_out toggles tc8l tc8h tc8h tc8l tc8l ...
zgp323h product specification ps023803-0305 functional description 44 into lo8; if it is a negative edge, data is put into hi8. from that point, one of the edge detect status bits (ctr1, d1; d0) is set, and an interrupt can be generated if enabled (ctr0, d2). meanwhile, t8 is loaded with ffh and starts counting again. if t8 reaches 0, the timeout status bit (ctr0, d5) is set, and an interrupt can be generated if enabled (ctr0, d1). t8 then continues counting from ffh (see figure 23 and figure 24). figure 23. demodulation mode count capture flowchart t8 (8-bit) count capture t8 enable (set by user) no yes edge present what kind of edge t8 hi8 no yes negative ffh t8 positive t8 lo8
zgp323h product specification ps023803-0305 functional description 45 figure 24. demodulation mode flowchart t8 (8-bit) demodulation mode t8 enable ctr0, d7 no yes ffh tc8 first edge present enable tc8 t8_enable bit set edge present t8 timeout set edge present status bit and trigger data capture int. if enabled set timeout status bit and trigger timeout int. if enabled continue counting disable tc8 no yes no yes yes yes no no
zgp323h product specification ps023803-0305 functional description 46 t16 transmit mode in normal or ping-pong mode, the output of t16 when not enabled, is depen- dent on ctr1, d0. if it is a 0, t16_out is a 1; if it is a 1, t16_out is 0. you can force the output of t16 to either a 0 or 1 whether it is enabled or not by program- ming ctr1 d3; d2 to a 10 or 11. when t16 is enabled, tc16h * 256 + tc16l is loaded, and t16_out is switched to its initial value (ctr1, d0). when t16 counts down to 0, t16_out is toggled (in normal or ping-pong mode), an interrupt (ctr2, d1) is generated (if enabled), and a status bit (ctr2, d5) is set. see figure 25. figure 25. 16-bit counter/timer circuits global interrupts override this function as described in ?interrupts? on page 50. if t16 is in single-pass mode, it is stopped at this point (see figure 26). if it is in modulo-n mode, it is loaded with tc16h * 256 + tc16l, and the counting con- tinues (see figure 27). you can modify the values in tc16h and tc16l at any time. the new values take effect when they are loaded. ctr2 d1 negative edge positive edge z8 ? data bus irq3 ctr2 d2 sclk z8 ? data bus ctr2 d4, d3 clock t16_out lo16 tc16h tc16l clock select 16-bit counter t16 hi16 note:
zgp323h product specification ps023803-0305 functional description 47 do not load these registers at the time the values are to be loaded into the counter/timer to ensure known operation. an initial count of 1 is not allowed. an initial count of 0 causes t16 to count from 0 to ffffh to fffeh . transition from 0 to ffffh is not a timeout condition. figure 26. t16_out in single-pass mode figure 27. t16_out in modulo-n mode t16 demodulation mode the user must program tc16l and tc16h to ffh . after t16 is enabled, and the first edge (rising, falling, or both depending on ctr1 d5; d4) is detected, t16 captures hi16 and lo16, re loads, and begins counting. if d6 of ctr2 is 0 when a subsequent edge (rising, falling, or both depending on ctr1, d5; d4) is detected during counting, the current count in t16 is complemented and put into hi16 and lo16. when data is captured, one of the edge detect status bits (ctr1, d1; d0) is set, and an interrupt is generated if enabled (ctr2, d2). t16 is loaded with ffffh and starts again. this t16 mode is generally used to meas ure space time, the length of time between bursts of carrier signal (marks). caution: tc16h*256+tc16l counts ?counter enable? command t16_out switches to its initial value (ctr1 d0) t16_out toggles, timeout interrupt tc16h*256+tc16l tc16h*256+tc16l tc16h*256+tc16l t16_out toggles, timeout interrupt t16_out toggles, timeout interrupt ?counter enable? command, t16_out switches to its initial value (ctr1 d0) tc16_out ...
zgp323h product specification ps023803-0305 functional description 48 if d6 of ctr2 is 1 t16 ignores the subsequent edges in th e input signal and continues counting down. a timeout of t8 causes t16 to capture its current value and generate an interrupt if enabled (ctr2, d2). in this case, t16 does not reload and continues counting. if the d6 bit of ctr2 is toggled (by writing a 0 then a 1 to it), t16 cap- tures and reloads on the next edge (rising, falling, or both depending on ctr1, d5; d4), continuing to ignore subsequent edges. this t16 mode generally measures mark time , the length of an active carrier sig- nal burst. if t16 reaches 0, t16 continues counting from ffffh . meanwhile, a status bit (ctr2 d5) is set, and an interrupt timeout can be generated if enabled (ctr2 d1). ping-pong mode this operation mode is only valid in tr ansmit mode. t8 and t16 must be pro- grammed in single-pass mode (ctr0, d6; ctr2, d6), and ping-pong mode must be programmed in ctr1, d3; d2. the user can begin the operation by enabling either t8 or t16 (ctr0, d7 or ct r2, d7). for example, if t8 is enabled, t8_out is set to this initial value (ctr1, d1). according to t8_out's level, tc8h or tc8l is loaded into t8. after the terminal count is reached, t8 is dis- abled, and t16 is enabled. t16_out then swit ches to its initial value (ctr1, d0), data from tc16h and tc16l is loaded, and t16 starts to count. after t16 reaches the terminal count, it stops, t8 is enabl ed again, repeating the entire cycle. inter- rupts can be allowed when t8 or t16 reaches terminal control (ctr0, d1; ctr2, d1). to stop the ping-pong operation, write 00 to bits d3 and d2 of ctr1. see figure 28. enabling ping-pong operation while the counter/timers are running might cause intermittent counter/timer function. disable the counter/timers and reset the status flags before instituting this operation. note:
zgp323h product specification ps023803-0305 functional description 49 figure 28. ping-pong mode diagram initiating ping-pong mode first, make sure both counter/timers are not running. set t8 into single-pass mode (ctr0, d6), set t16 into single-pass mode (ctr2, d6), and set the ping-pong mode (ctr1, d2; d3). these instructions can be in random order. finally, start ping-pong mode by enabling either t8 (ctr0, d7) or t16 (ctr2, d7). see figure 29. figure 29. output circuit the initial value of t8 or t16 must not be 1 . stopping the timer and restarting the timer reloads the initial value to avoid an unknown previous value. enable tc8 enable timeout tc16 ping-pong ctr1 d3,d2 timeout t16_out mux ctr1 d3 t8_out p34 and/or/nor/nand logic mux mux mux p35 p36 p34_internal ctr1 d5, d4 p36_internal p35_internal ctr1, d2 ctr0 d0 ctr1 d6 ctr2 d0
zgp323h product specification ps023803-0305 functional description 50 during ping-pong mode the enable bits of t8 and t16 (ctr0, d7; ctr2, d7) are set and cleared alter- nately by hardware. the timeout bits (ctr 0, d5; ctr2, d5) are set every time the counter/timers reach the terminal count. interrupts the zgp323h features six different interrupts (table 19). the interrupts are maskable and prioritized (figure 30). the si x sources are divided as follows: three sources are claimed by port 3 lines p33?p31, two by the counter/timers (table 19) and one for low voltage detection. the interrupt mask register (globally or individually) enables or disables the six interrupt requests. the source for irq is determined by bit 1 of the port 3 mode register (p3m). when in digital mode, pin p33 is the source. when in analog mode the output of the stop mode recovery source logic is used as the source for the interrupt. see figure 35, stop mode recovery source, on page 59.
zgp323h product specification ps023803-0305 functional description 51 figure 30. interrupt block diagram low-voltage detection timer 8 timer 16 interrupt edge select imr ipr priority logic irq 5 irq2 irq0 irq1 irq3 irq4 irq5 p31 p32 irq register d6, d7 global interrupt enable interrupt request vector select d1 of p3m register p33 0 1 stop mode recovery source
zgp323h product specification ps023803-0305 functional description 52 when more than one interrupt is pending, priorities are resolved by a programma- ble priority encoder controlled by the inte rrupt priority register. an interrupt machine cycle activates when an interrupt request is granted. as a result, all sub- sequent interrupts are disabled, and the program counter and status flags are saved. the cycle then branches to the program memory vector location reserved for that interrupt. all zgp323h interrupts are vectored through locations in the program memory. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked, and the inter- rupt request register is polled to determine which of the interrupt requests require service. an interrupt resulting from an1 is mapped into irq2, and an interrupt from an2 is mapped into irq0. interrupts irq2 and irq0 can be rising, falling, or both edge triggered. these interrupts are programmabl e by the user. the software can poll to identify the state of the pin. programming bits for the interrupt edge select are located in the irq register (r250), bits d7 and d6. the configuration is indicated in table 20. table 19. interrupt types, sources, and vectors name source vector location comments irq0 p32 0,1 external (p32), ris ing, falling edge triggered irq1 p33 2,3 external (p33), falling edge triggered irq2 p31, t in 4,5 external (p31), rising, falling edge triggered irq3 t16 6,7 internal irq4 t8 8,9 internal irq5 lvd 10,11 internal table 20. irq register irq interrupt edge d7 d6 irq2 (p31) irq0 (p32) 00f f 01f r 10r f 11r/f r/f note: f = falling edge; r = rising edge
zgp323h product specification ps023803-0305 functional description 53 clock the device?s on-chip oscillator has a hi gh-gain, parallel-resonant amplifier, for connection to a crystal or ceramic resonator , or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal must be at cut, 1 mhz to 8 mhz maximum, with a series resistance (rs) less than or equal to 100 ? . the on-chip oscillator can be driven with a suitable external clock source. the crystal must be connected across xtal1 and xtal2 using the recommended capacitors (capacitance greater than or equal to 22 pf) from each pin to ground. figure 31. oscillator configuration c1 c2 xtal1 xtal2 xtal1 xtal2 crystal c1, c2 = 33pf typ * f = 8mhz * preliminary value including pin parasitics external clock xtal1 xtal2 ceramic resonator f = 8mhz
zgp323h product specification ps023803-0305 functional description 54 power-on reset a timer circuit clocked by a dedicated on-board rc-oscillator is used for the power-on reset (por) timer func tion. the por time allows v dd and the oscilla- tor circuit to stabilize before instruction execution begins. the por timer circuit is a one-shot timer triggered by one of three conditions: ? power fail to power ok status, including waking up from v bo standby ? stop-mode recovery (if d5 of smr = 1) ? wdt timeout the por timer is 2.5 ms minimum. bit 5 of the stop-mode register determines whether the por timer is bypassed after stop-mode recovery (typical for external clock). halt mode this instruction turns off the internal cpu clock, but not the xtal oscillation. the counter/timers and external interrupts ir q0, irq1, irq2, irq3, irq4, and irq5 remain active. the devices are recovered by interrupts, either externally or inter- nally generated. an interrupt request must be executed (enabled) to exit halt mode. after the interrupt service routine, the program continues from the instruc- tion after halt mode. stop mode this instruction turns off the internal cloc k and external crystal oscillation, reduc- ing the standby current to 10 a or less. stop mode is terminated only by a reset, such as wdt timeout, por, smr or external reset. this condition causes the processor to restart the application program at address 000ch . to enter stop (or halt) mode, first flush the instructi on pipeline to avoid suspending execution in mid-instruction. execute a nop (opcode = ffh ) immediately before the appro- priate sleep instruction, as follows:
zgp323h product specification ps023803-0305 functional description 55 ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode port configuration register the port configuration (pcon) register (figure 32) configures the comparator output on port 3. it is located in the expanded register 2 at bank f, location 00. pcon(fh)00h figure 32. port configuration register (pcon) (write only) comparator output port 3 (d0) bit 0 controls the comparator used in port 3. a 1 in this location brings the compar- ator outputs to p34 and p37, and a 0 releases the port to its standard i/o configu- ration. port 1 output mode (d1) bit 1 controls the output mode of port 1. a 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 p34, p37 standard output* 1 p34, p37 comparator output port 1 0: open-drain 1: push-pull* port 0 0: open-drain 1: push-pull* reserved (must be 1) * default setting after reset
zgp323h product specification ps023803-0305 functional description 56 port 0 output mode (d2) bit 2 controls the output mode of port 0. a 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. stop-mode recovery register (smr) this register selects the clock divide value and determines the mode of stop mode recovery (figure 33). all bits are write only except bit 7, which is read only. bit 7 is a flag bit that is hardware set on the condition of stop recovery and reset by a power-on cycle. bit 6 controls whether a low level or a high level at the xor- gate input (figure 35 on page 59) is requir ed from the recovery source. bit 5 con- trols the reset delay after recovery. bits d2, d3, and d4 of the smr register spec- ify the source of the stop mode recovery signal. bits d0 determines if sclk/ tclk are divided by 16 or not. the smr is located in bank f of the expanded register group at address 0bh .
zgp323h product specification ps023803-0305 functional description 57 smr(0f)0bh figure 33. stop mode recovery register sclk/tclk divide-by-16 select (d0) d0 of the smr controls a divide-by-16 prescaler of sclk/tclk (figure 34). this control selectively reduces device power consumption during normal processor execution (sclk control) and/or halt mode (where tclk sources interrupt logic). after stop mode recovery, this bit is set to a 0. d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 off * * 1 on reserved (must be 0) stop-mode recovery source 000 por only * 001 reserved 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 stop delay 0 off 1 on * * * * stop recovery level * * * 0 low * 1 high stop flag 0 por * 1 stop recovery * * * default after power on reset or watch-dog reset * * default setting after reset and stop mode recovery * * * at the xor gate input * * * * default setting after reset. must be 1 if using a crystal or resonator clock source.
zgp323h product specification ps023803-0305 functional description 58 figure 34. sclk circuit stop-mode recovery source (d2, d3, and d4) these three bits of the smr specify the wake-up source of the stop recovery (figure 35 and table 22). stop-mode recovery register 2?smr2(f)0dh table 21 lists and briefly describes the fields for this register. table 21. smr2(f)0dh:stop mode recovery register 2* field bit position value description reserved 7------- 0 reserved (must be 0) recovery level -6------ w0 ? 1 low high reserved --5----- 0 reserved (must be 0) source ---432-- w 000 ? 001 010 011 100 101 110 111 a. por only b. nand of p23?p20 c. nand of p27?p20 d. nor of p33?p31 e. nand of p33?p31 f. nor of p33?p31, p00, p07 g. nand of p33?p31, p00, p07 h. nand of p33?p31, p22?p20 reserved ------10 00 reserved (must be 0) notes: * port pins configured as outputs are ignored as a smr recovery source. ? indicates the value upon power-on reset sclk tclk smr, d0 2 osc 16
zgp323h product specification ps023803-0305 functional description 59 figure 35. stop mode recovery source smr2 d4 d3 d2 100 smr2 d4 d3 d2 111 smr d4d3d2 010 smr d4d3d2 111 smr d4d3d2 101 smr d4d3d2 100 smr d4d3d2 011 smr d4d3d2 000 smr d4d3d2 110 vcc p31 p32 p33 p27 p20 p23 p20 p27 smr2 d4 d3 d2 001 smr2 d4 d3 d2 000 smr2 d4 d3 d2 010 smr2 d4 d3 d2 011 smr2 d4 d3 d2 101 smr2 d4 d3 d2 110 vcc p20 p23 p20 p27 p31 p32 p33 p31 p32 p33 p31 p32 p33 p00 p07 p31 p32 p33 p00 p07 p31 p32 p33 p20 p21 smr d6 smr2 d6 to reset and wdt circuitry (active low)
zgp323h product specification ps023803-0305 functional description 60 any port 2 bit defined as an output drives the corresponding input to the default state. this condition allows the remaining inputs to control the and/or function. refer to smr2 register on page 61 for other recover sources. stop mode recovery delay select (d5) this bit, if low, disables the t por delay after stop mode recovery. the default configuration of this bit is 1. if the ?fast? wake up is selected, the stop mode recovery source must be kept active for at least 5 tpc. this bit must be set to 1 if using a crystal or resonator clock source. the t por delay allows the clock source to stabilize before executing instructions. stop mode recovery edge select (d6) a 1 in this bit position indicates that a high level on any one of the recovery sources wakes the device from stop mode. a 0 indicates low level recovery. the default is 0 on por. cold or warm start (d7) this bit is read only. it is set to 1 when the device is recovered from stop mode. the bit is set to 0 when the device rese t is other than stop mode recovery (smr). table 22. stop mode recovery source smr:432 operation d4 d3 d2 description of action 0 0 0 por and/or external reset recovery 001reserved 010p31 transition 011p32 transition 100p33 transition 101p27 transition 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27 note: note:
zgp323h product specification ps023803-0305 functional description 61 stop mode recovery register 2 (smr2) this register determines the mode of stop mode recovery for smr2 (figure 36). smr2(0f)dh figure 36. stop mode recovery register 2 ((0f)dh:d2?d4, d6 write only) if smr2 is used in conjunction with smr, either of the specified events causes a stop mode recovery. port pins configured as outputs are ignored as an smr or smr2 recovery source. for example, if the nand or p23?p20 is selected as the recovery source and p20 is configured as an output, the remaining smr pins (p23?p21) form the nand equation. d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 0) stop-mode recovery source 2 000 por only * 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p2 3, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level * * 0low * 1 high reserved (must be 0) note: if used in conjunction with sm r, either of the two specified ev ents causes a stop-mode recovery. * default setting after reset * * at the xor gate input note:
zgp323h product specification ps023803-0305 functional description 62 watch-dog timer mode register (wdtmr) the watch-dog timer (wdt) is a retriggerable one-shot timer that resets the z8 ? cpu if it reaches its terminal count. th e wdt must initially be enabled by execut- ing the wdt instruction. on subsequent ex ecutions of the wdt instruction, the wdt is refreshed. the wdt circuit is driven by an on-board rc-oscillator. the wdt instruction affects the zero (z), sign (s), and overflow (v) flags. the por clock source the internal rc-oscillator. bits 0 and 1 of the wdt register control a tap circuit that determines th e minimum timeout period. bit 2 determines whether the wdt is active during halt, and bit 3 determines wdt activity during stop. bits 4 through 7 are reserved (figure 37). this register is accessible only during the first 60 processor cycles (120 xtal clocks) from the execution of the first instruction after power-on-reset, watch-dog reset, or a stop-mode recovery (figure 36). after this point, the register cannot be modified by any means (intentional or otherwise). the wdtmr cannot be read. the register is located in bank f of the expanded register group at address location 0fh . it is organized as shown in figure 37. wdtmr(0f)0fh figure 37. watch-dog timer mode register (write only) wdt time select (d0, d1) this bit selects the wdt time period. it is configured as indicated in table 23. d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc 00 5 ms min. 01* 10 ms min. 10 20 ms min. 11 80 ms min. wdt during halt 0off 1on * wdt during stop 0off 1on * reserved (must be 0) * default setting after reset
zgp323h product specification ps023803-0305 functional description 63 wdtmr during halt (d2) this bit determines whether or not the wd t is active during halt mode. a 1 indi- cates active during halt. the default is 1. see figure 38. figure 38. resets and wdt table 23. watch-dog timer time select d1 d0 timeout of internal rc-oscillator 005ms min. 0 1 10ms min. 1 0 20ms min. 1 1 80ms min. - * clr1 and clr2 enable the wdt/por and 18 clock reset timers respectively upon a low-to- + from stop mode recovery stop delay select 5 clock *clr2 18 clock reset rese wdt por 5 ms 10 ms 20 ms 80 cl *clr wdt/por counter chain internal rc oscillator. wdt v dd low operating vbo v dd interna l rese t 12-ns glitch xtal
zgp323h product specification ps023803-0305 functional description 64 wdtmr during stop (d3) this bit determines whether or not th e wdt is active during stop mode. because the xtal clock is stopped during stop mode, the on-board rc has to be selected as the clock source to the wdt/por counter. a 1 indicates active during stop. the default is 1. eprom selectable options there are seven eprom selectable opti ons to choose from based on rom code requirements. these options are listed in table 24. voltage brown-out/standby an on-chip voltage comparator checks that the v dd is at the required level for correct operation of the device. reset is globally driven when v dd falls below v bo . a small drop in v dd causes the xtal1 and xtal2 circuitry to stop the crystal or resonator clock. if the v dd is allowed to stay above v ram , the ram content is pre- served. when the power level is returned to above v bo , the device performs a por and functions normally. table 24. eprom selectable options port 00?03 pull-ups on/off port 04?07 pull-ups on/off port 10?13 pull-ups on/off port 14?17 pull-ups on/off port 20?27 pull-ups on/off eprom protection on/off watch-dog timer at power-on reset on/off
zgp323h product specification ps023803-0305 functional description 65 low-voltage detection register?lvd(d)0ch voltage detection does not work at stop mode. it must be disabled during stop mode in order to reduce current. do not modify register p01m while checking a low-voltage condition. switching noise of both ports 0 and 1 together might trigger the lvd flag. voltage detection and flags the voltage detection register (lvd, register 0ch at the expanded register bank 0dh ) offers an option of monitoring the v cc voltage. the voltage detection is enabled when bit 0 of lvd register is set. once voltage detection is enabled, the the v cc level is monitored in real time. the flags in the lvd register valid 20us after voltage detection is enabled. the hvd flag (bit 2 of the lvd register) is set only if v cc is higher than v hvd. the lvd flag (bit 1 of the lvd register) is set only if v cc is lower than the v lvd . when voltage detection is enabled, the lvd flag also triggers irq5. the irq bit 5 latches the low voltage condition until it is cleared by instructions or reset. the irq5 interrupt is served if it is enabled in the imr register. otherwise, bit 5 of irq register is latched as a flag only. if it is necessary to receive an lvd interrupt upon power-up at an operating voltage lower than the low battery detect threshold, enable interrupts using the enable interrupt instruction (ei) prior to enabling the voltage detection. field bit position description lvd 76543--- reserved no effect -----2-- r 1 0* hvd flag set hvd flag reset ------1- r 1 0* lvd flag set lvd flag reset -------0 r/w 1 0* enable vd disable vd * default after por note: note: notes:
zgp323h product specification ps023803-0305 expanded register file control registers (0d) 66 expanded register file control registers (0d) the expanded register file control registers (0d) are depicted in figure 39 through figure 43. figure 39. tc8 control register ((0d)o0h: read/write except where noted) ctr0(0d)00h d7 d6 d5 d4 d3 d2 d1 d0 0 p34 as port output * 1 timer8 output 0 disable t8 timeout interrupt * * 1 enable t8 timeout interrupt 0 disable t8 data capture interrupt * * 1 enable t8 data capture interrupt 00 sclk on t8* * 01 sclk/2 on t8 10 sclk/4 on t8 11 sclk/8 on t8 r 0 no t8 counter timeout * * r 1 t8 counter timeout occurred w 0 no effect w 1 reset flag to 0 0 modulo-n * 1 single pass r 0 t8 disabled * r 1 t8 enabled w0 stop t8 w 1 enable t8 * default setting after reset. * * default setting after reset.. not reset with a stop-mode recovery.
zgp323h product specification ps023803-0305 expanded register file control registers (0d) 67 figure 40. t8 and t16 common control functions ((0d)01h: read/write) ctr1(0d)01h d7 d6 d5 d4 d3 d2 d1 d0 transmit mode* r/w 0 t16_out is 0 initially 1 t16_out is 1 initially demodulation mode r 0 no falling edge detection r 1 falling edge detection w 0 no effect w 1 reset flag to 0 transmit mode* r/w 0 t8_out is 0 initially* 1 t8_out is 1 initially demodulation mode r 0 no rising edge detection r 1 rising edge detection w 0 no effect w 1 reset flag to 0 transmit mode* 0 0 normal operation* 0 1 ping-pong mode 1 0 t16_out = 0 1 1 t16_out = 1 demodulation mode 0 0 no filter 0 1 4 sclk cycle filter 1 0 8 sclk cycle filter 11reserved transmit mode/t8/t16 logic 0 0 and** 01or 1 0 nor 1 1 nand demodulation mode 0 0 falling edge detection 01rising edge detection 1 0 both edge detection 11reserved transmit mode* 0 p36 as port output * 1 p36 as t8/t16_out demodulation mode 0 p31 as demodulator input 1 p20 as demodulator input transmit/demodulation mode 0 transmit mode * 1 demodulation mode * default setting after reset **default setting after reset.. not reset with a stop-mode recovery.
zgp323h product specification ps023803-0305 expanded register file control registers (0d) 68 take care in differentiating the transmit mode from demodulation mode. depending on which of these two modes is operating, the ctr1 bit has different functions. changing from one mode to another cannot be performed without disabling the counter/timers. notes:
zgp323h product specification ps023803-0305 expanded register file control registers (0d) 69 ctr2(0d)02h figure 41. t16 control register ((0d) 2h: read/write except where noted) d7 d6 d5 d4 d3 d2 d1 d0 0 p35 is port output * 1 p35 is tc16 output 0 disable t16 timeout interrupt 1 enable t16 timeout interrupt 0 disable t16 data capture interrupt 1 enable t16 data capture interrupt 0 0 sclk on t16 0 1 sclk/2 on t16 1 0 sclk/4 on t16 1 1 sclk/8 on t16 r 0 no t16 timeout r 1 t16 timeout occurs w 0 no effect w 1 reset flag to 0 transmit mode 0 modulo-n for t16 1 single pass for t16 demodulator mode 0 t16 recognizes edge 1 t16 does not recognize edge r 0 t16 disabled * r 1 t16 enabled w 0 stop t16 w1enable t16 * default setting after reset ** default setting after reset. not reset with a stop- mode recovery.
zgp323h product specification ps023803-0305 expanded register file control registers (0d) 70 ctr3(0d)03h figure 42. t8/t16 control register (0d)03h: read/write (except where noted) d7 d6 d5 d4 d3 d2 d1 d0 reserved no effect when written always reads 11111 sync mode 0* disable sync mode** 1 enable sync mode t 8 enable r 0* t 8 disabled r 1 t 8 enabled w0 stop t 8 w1 enable t 8 t 16 enable r 0* t 16 disabled r 1 t 16 enabled w 0 stop t 16 w 1 enable t 16 * default setting after reset. ** default setting after re set. not reset with a stop mode recovery.
zgp323h product specification ps023803-0305 expanded register file control registers (0f) 71 lvd(0d)0ch figure 43. voltage detection register do not modify register p01m while checking a low-voltage condition. switching noise of both ports 0 and 1 together might trigger the lvd flag. expanded register file control registers (0f) the expanded register file control registers (0f) are depicted in figures 44 through figure 57. d7 d6 d5 d4 d3 d2 d1 d0 voltage detection 0: disable * 1: enable lvd flag (read only) 0: lvd flag reset * 1: lvd flag set hvd flag (read only) 0: hvd flag reset * 1: hvd flag set reserved (must be 0) * default setting after reset. note:
zgp323h product specification ps023803-0305 expanded register file control registers (0f) 72 pcon(0f)00h figure 44. port configuration register (pcon)(0f)00h: write only) d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 p34, p37 standard output * 1 p34, p37 comparator output port 1 0: open-drain 1: push-pull* port 0 0: open-drain 1: push-pull * reserved (must be 1) * default setting after reset
zgp323h product specification ps023803-0305 expanded register file control registers (0f) 73 smr(0f)0bh figure 45. stop mode recovery register ((0f)0bh: d6?d0=write only, d7=read only) d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 off * 1 on reserved (must be 0) stop-mode recovery source 000 por only * 001 reserved 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0?3 111 p2 nor 0?7 stop delay 0off 1 on * * * * stop recovery level * * * 0 low * 1 high stop flag 0 por * * * * * 1 stop recovery * * * default setting after reset * * set after stop mode recovery * * * at the xor gate input * * * * default setting after reset. must be 1 if using a crystal or resonator clock source. * * * * * default setting after power on re set. not reset with a stop mode recovery.
zgp323h product specification ps023803-0305 expanded register file control registers (0f) 74 smr2(0f)0dh figure 46. stop mode recovery register 2 ((0f)0dh:d2?d4, d6 write only) d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 0) stop-mode recovery source 2 000 por only * 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p2 3, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level * * 0low 1 high reserved (must be 0) note: if used in conjunction with sm r, either of the two specified ev ents causes a stop-mode recovery. * default setting after reset. not reset with a stop mode recovery. * * at the xor gate input
zgp323h product specification ps023803-0305 standard control registers 75 wdtmr(0f)0fh figure 47. watch-dog timer register ((0f) 0fh: write only) standard control registers r246 p2m(f6h) figure 48. port 2 mode register (f6h: write only) d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc 00 5 ms min. 01* 10 ms min. 10 20 ms min. 11 80 ms min. wdt during halt 0off 1on * wdt during stop 0off 1on * reserved (must be 0) * default setting after reset. not reset with a stop mode recovery. d7 d6 d5 d4 d3 d2 d1 d0 p27?p20 i/o definition 0 defines bit as output 1 defines bit as input * * default setting after reset. not reset with a stop mode recovery.
zgp323h product specification ps023803-0305 standard control registers 76 r247 p3m(f7h) figure 49. port 3 mode register (f7h: write only) d7 d6 d5 d4 d3 d2 d1 d0 0: port 2 open drain * 1: port 2 push-pull 0= p31, p32 digital mode* 1= p31, p32 analog mode reserved (must be 0) * default setting after reset. not reset with a stop mode recovery.
zgp323h product specification ps023803-0305 standard control registers 77 r248 p01m(f8h) figure 50. port 0 and 1 mode register (f8h: write only) d7 d6 d5 d4 d3 d2 d1 d0 p00?p03 mode 0: output 1: input * reserved (must be 0) reserved (must be 1) p17?p10 mode 0: byte output 1: byte input* reserved (must be 0) p07?p04 mode 0: output 1: input * reserved (must be 0) * default setting after reset; only p00, p01 and p07 are available on 20-pin configurations.
zgp323h product specification ps023803-0305 standard control registers 78 r249 ipr(f9h) figure 51. interrupt priority register (f9h: write only) d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority 000 reserved 001 c > a > b 010 a > b >c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved irq1, irq4, priority (group c) 0: irq1 > irq4 1: irq4 > irq1 irq0, irq2, priority (group b) 0: irq2 > irq0 1: irq0 > irq2 irq3, irq5, priority (group a) 0: irq5 > irq3 1: irq3 > irq5 reserved; must be 0
zgp323h product specification ps023803-0305 standard control registers 79 r250 irq(fah) figure 52. interrupt request register (fah: read/write) r251 imr(fbh) figure 53. interrupt mask register (fbh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = t16 irq4 = t8 irq5 = lvd inter edge p31 p32 = 00 p31 p32 = 01 p31 p32 = 10 p31 p32 = 11 d7 d6 d5 d4 d3 d2 d1 d0 1 enables irq5?irq0 (d0 = irq0) reserved (must be 0) 0 master interrupt disable * 1 master interrupt enable * * * default setting after reset * * only by using ei, di inst ruction; di is required before changing the imr register
zgp323h product specification ps023803-0305 standard control registers 80 r252 flags(fch) figure 54. flag register (fch: read/write) r253 rp(fdh) figure 55. register pointer (fdh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign tag zero flag carry flag d7 d6 d5 d4 d3 d2 d1 d0 expanded register bank pointer working register pointer default setting after reset = 0000 0000
zgp323h product specification ps023803-0305 package information 81 r254 sph(feh) figure 56. stack pointer high (feh: read/write) r255 spl(ffh) figure 57. stack pointer low (ffh: read/write) package information package information for all versions of zgp323h is depicted in figures 59 through figure 68. d7 d6 d5 d4 d3 d2 d1 d0 general-purpose register d7 d6 d5 d4 d3 d2 d1 d0 stack pointer low byte (sp7?sp0)
zgp323h product specification ps023803-0305 package information 82 figure 58. 20-pin cdip package figure 59. 20-pin pdip package diagram
zgp323h product specification ps023803-0305 package information 83 figure 60. 20-pin soic package diagram
zgp323h product specification ps023803-0305 package information 84 figure 61. 20-pin ssop package diagram
zgp323h product specification ps023803-0305 package information 85 figure 62. 28-pin soic package diagram
zgp323h product specification ps023803-0305 package information 86 figure 63. 28-pin cdip package diagram figure 64. 28-pin pdip package diagram
zgp323h product specification ps023803-0305 package information 87 figure 65. 28-pin ssop package diagram figure 66. 40-pin pdip package diagram symbol a a1 b c a2 e millimeter inch min max min max 1.73 0.05 1.68 0.25 5.20 0.65 typ 0.09 10.07 7.65 0.63 1.86 0.0256 typ 0.13 10.20 1.73 7.80 5.30 1.99 0.21 1.78 0.75 0.068 0.002 0.066 0.010 0.205 0.004 0.397 0.301 0.025 0.073 0.005 0.068 0.209 0.006 0.402 0.307 0.030 0.078 0.008 0.070 0.015 0.212 0.008 0.407 0.311 0.037 0.38 0.20 10.33 5.38 7.90 0.95 nom nom d e h l controlling dimensions: mm leads are coplanar within .004 inches. h c detail a e d 28 15 114 seating plane a2 e a q1 a1 b l 0 - 8 detail 'a'
zgp323h product specification ps023803-0305 package information 88 figure 67. 40-pin cdip package diagram
zgp323h product specification ps023803-0305 package information 89 figure 68. 48-pin ssop package design check with zilog on the actual bonding diagram and coordinate for chip-on-board assembly. controlling dimensions : mm leads are coplanar within .004 inch d e h a1 a2 a e seating plane b 48 25 c detail a 0-8? l 1 24 note:
zgp323h product specification ps023803-0305 ordering information 90 ordering information 32kb standard temperature: 0 to +70c part number description p art number description zgp323hsh4832c 48-pin ssop 32k otp zgp323hss2832c 28-pin soic 32k otp zgp323hsp4032c 40-pin pdip 32k otp zgp323hsh2032c 20-pin ssop 32k otp zgp323hsk2832e 28-pin cdip 32k otp zgp323hsk2032e 20-pin cdip 32k otp zgp323hsk4032e 40-pin cdip 32k otp zgp323hsp2032c 20-pin pdip 32k otp zgp323hsh2832c 28-pin ssop 32k otp zgp323hss2032c 20-pin soic 32k otp zgp323hsp2832c 28-pin pdip 32k otp 32kb extended temperature: -40 to +105c part number description p art number description zgp323heh4832c 48-pin ssop 32k otp zgp323hes2832c 28-pin soic 32k otp zgp323hep4032c 40-pin pdip 32k otp zgp323heh2032c 20-pin ssop 32k otp zgp323heh2832c 28-pin ssop 32k otp ZGP323HEP2032C 20-pin pdip 32k otp zgp323hep2832c 28-pin pdip 32k otp zgp323hes2032c 20-pin soic 32k otp 32kb automotive temperature: -40 to +125c part number description p art number description zgp323hah4832c 48-pin ssop 32k otp zgp323has2832c 28-pin soic 32k otp zgp323hap4032c 40-pin pdip 32k otp zgp323hah2032c 20-pin ssop 32k otp zgp323hah2832c 28-pin ssop 32k otp zgp323hap2032c 20-pin pdip 32k otp zgp323hap2832c 28-pin pdip 32k otp zgp323has2032c 20-pin soic 32k otp replace c with g for lead-free packaging
zgp323h product specification ps023803-0305 ordering information 91 16kb standard temperature: 0 to +70c part number description part number description zgp323hsh4816c 48-pin ssop 16k otp zgp323hss2816c 28-pin soic 16k otp zgp323hsp4016c 40-pin pdip 16k otp zgp323hsh2016c 20-pin ssop 16k otp zgp323hsh2816c 28-pin ssop 16k otp zgp323hsp2016c 20-pin pdip 16k otp zgp323hsp2816c 28-pin pdip 16k otp zgp323hss2016c 20-pin soic 16k otp 16kb extended temperature: -40 to +105c part number description part number description zgp323heh4816c 48-pin ssop 16k otp zgp323hes2816c 28-pin soic 16k otp zgp323hep4016c 40-pin pdip 16k otp zgp323heh2016c 20-pin ssop 16k otp zgp323heh2816c 28-pin ssop 16k otp zgp323hep2016c 20-pin pdip 16k otp zgp323hep2816c 28-pin pdip 16k otp zgp323hes2016c 20-pin soic 16k otp 16kb automotive temperature: -40 to +125c part number description part number description zgp323hah4816c 48-pin ssop 16k otp zgp323has2816c 28-pin soic 16k otp zgp323hap4016c 40-pin pdip 16k otp zgp323hah2016c 20-pin ssop 16k otp zgp323hah2816c 28-pin ssop 16k otp zgp323hap2016c 20-pin pdip 16k otp zgp323hap2816c 28-pin pdip 16k otp zgp323has2016c 20-pin soic 16k otp replace c with g for lead-free packaging
zgp323h product specification ps023803-0305 ordering information 92 8kb standard temperature: 0 to +70c part number description part number description zgp323hsh4808c 48-pin ssop 8k otp zgp323hss2808c 28-pin soic 8k otp zgp323hsp4008c 40-pin pdip 8k otp zgp323hsh2008c 20-pin ssop 8k otp zgp323hsh2808c 28-pin ssop 8k otp zgp323hsp2008c 20-pin pdip 8k otp zgp323hsp2808c 28-pin pdip 8k otp zgp323hss2008c 20-pin soic 8k otp 8kb extended temperature: -40 to +105c part number description part number description zgp323heh4808c 48-pin ssop 8k otp zgp323hes2808c 28-pin soic 8k otp zgp323hep4008c 40-pin pdip 8k otp zgp323heh2008c 20-pin ssop 8k otp zgp323heh2808c 28-pin ssop 8k otp zgp323hep2008c 20-pin pdip 8k otp zgp323hep2808c 28-pin pdip 8k otp zgp323hes2008c 20-pin soic 8k otp 8kb automotive temperature: -40 to +125c part number description part number description zgp323hah4808c 48-pin ssop 8k otp zgp323has2808c 28-pin soic 8k otp zgp323hap4008c 40-pin pdip 8k otp zgp323hah2008c 20-pin ssop 8k otp zgp323hah2808c 28-pin ssop 8k otp zgp323hap2008c 20-pin pdip 8k otp zgp323hap2808c 28-pin pdip 8k otp zgp323has2008c 20-pin soic 8k otp replace c with g for lead-free packaging
zgp323h product specification ps023803-0305 ordering information 93 4kb standard temperature: 0 to +70c part number description part number description zgp323hsh4804c 48-pin ssop 4k otp zgp 323hss2804c 28-pin soic 4k otp zgp323hsp4004c 40-pin pdip 4k otp zgp323hsh2004c 20-pin ssop 4k otp zgp323hsh2804c 28-pin ssop 4k otp zgp 323hsp2004c 20-pin pdip 4k otp zgp323hsp2804c 28-pin pdip 4k otp z gp323hss2004c 20-pin soic 4k otp 4kb extended temperature: -40 to +105c part number description part number description zgp323heh4804c 48-pin ssop 4k otp zgp 323hes2804c 28-pin soic 4k otp zgp323hep4004c 40-pin pdip 4k otp zgp323heh2004c 20-pin ssop 4k otp zgp323heh2804c 28-pin ssop 4k otp zgp 323hep2004c 20-pin pdip 4k otp zgp323hep2804c 28-pin pdip 4k otp z gp323hes2004c 20-pin soic 4k otp 4kb automotive temperature: -40 to +125c part number description part number description zgp323hah4804c 48-pin ssop 4k otp zgp 323has2804c 28-pin soic 4k otp zgp323hap4004c 40-pin pdip 4k otp zgp323hah2004c 20-pin ssop 4k otp zgp323hah2804c 28-pin ssop 4k otp zgp 323hap2004c 20-pin pdip 4k otp zgp323hap2804c 28-pin pdip 4k otp z gp323has2004c 20-pin soic 4k otp replace c with g for lead-free packaging additional components part number description part number description zgp323ice01zem (for 3.6v emulation only) emulator/programmer zgp32300100zpr (ethernet) programming system zgp32300200zpr (usb) programming system
zgp323h product specification ps023803-0305 ordering information 94 for fast results, contact your local zilog sales office for assistance in ordering the part desired. codes zg = zilog general purpose family p = otp 323 = family designation h = high voltage t = temparature s = standard 0 to +70c e = extended -40 to +105c a = automotive -40 to +125c p = package type: k = cdip p = pdip h = ssop s = soic ## = number of pins cc = memory size m = molding compound c = standard plastic packaging molding compound g = green plastic molding compound e = standard cer dip flow
zgp323h product specification ps023803-0305 ordering information 95 example zg p 323 h t p 48 32 c molding compound memory size number of pins package type: e = cdip p = pdip h = ssop s = soic temperature: s = standard e = extended a = automotive voltage: h = high family designation otp zilog general-purpose family
zgp323h z8 ? otp microcontroller with ir timers ps023803-0305 p r e l i m i n a r y index 96 numerics 16-bit counter/timer circuits 46 20-pin dip package diagram 82 20-pin ssop package diagram 84 28-pin dip package diagram 86 28-pin soicpackage diagram 85 28-pin ssop package diagram 87 40-pin dip package diagram 87 48-pin ssop package diagram 89 8-bit counter/timer circuits 42 a absolute maximum ratings 10 ac characteristics 16 timing diagram 16 address spaces, basic 2 architecture 2 expanded register file 28 b basic address spaces 2 block diagram, zlp32300 functional 3 c capacitance 11 characteristics ac 16 dc 11 clock 53 comparator inputs/outputs 25 configuration port 0 19 port 1 20 port 2 21 port 3 22 port 3 counter/timer 24 counter/timer 16-bit circuits 46 8-bit circuits 42 brown-out voltage/standby 64 clock 53 demodulation mode c ount capture flow- chart 44 demodulation mode flowchart 45 eprom selectable options 64 glitch filter circuitry 40 halt instruction 54 input circuit 40 interrupt block diagram 51 interrupt types, sources and vectors 52 oscillator configuration 53 output circuit 49 ping-pong mode 48 port configuration register 55 resets and wdt 63 sclk circuit 58 stop instruction 54 stop mode recovery register 57 stop mode recovery register 2 61 stop mode recovery source 59 t16 demodulation mode 47 t16 transmit mode 46 t16_out in modulo-n mode 47 t16_out in single-pass mode 47 t8 demodulation mode 43 t8 transmit mode 40 t8_out in modulo-n mode 43 t8_out in single-pass mode 43 transmit mode flowchart 41 voltage detection and flags 65 watch-dog timer mode register 62 watch-dog timer time select 63 ctr(d)01h t8 and t16 common functions 35 d dc characteristics 11 demodulation mode count capture flowchart 44 flowchart 45 t16 47 t8 43 description functional 25 general 2
zgp323h z8 ? otp microcontroller with ir timers ps023803-0305 p r e l i m i n a r y index 97 pin 4 e eprom selectable options 64 expanded register file 26 expanded register file architecture 28 expanded register file control registers 71 flag 80 interrupt mask register 79 interrupt priority register 78 interrupt request register 79 port 0 and 1 mode register 77 port 2 configuration register 75 port 3 mode register 76 port configuration register 75 register pointer 80 stack pointer high register 81 stack pointer low register 81 stop-mode recove ry register 73 stop-mode recovery register 2 74 t16 control register 69 t8 and t16 common c ontrol functions reg- ister 67 t8/t16 control register 70 tc8 control register 66 watch-dog timer register 75 f features standby modes 1 functional description counter/timer functional blocks 40 ctr(d)01h register 35 ctr0(d)00h register 33 ctr2(d)02h register 37 ctr3(d)03h register 39 expanded register file 26 expanded register file architecture 28 hi16(d)09h register 32 hi8(d)0bh register 32 l08(d)0ah register 32 l0i6(d)08h register 32 program memory map 26 ram 25 register description 65 register file 30 register pointer 29 register pointer detail 31 smr2(f)0d1h register 40 stack 31 tc16h(d)07h register 32 tc16l(d)06h register 33 tc8h(d)05h register 33 tc8l(d)04h register 33 g glitch filter circuitry 40 h halt instruction, counter/timer 54 i input circuit 40 interrupt block diagram, counter/timer 51 interrupt types, sources and vectors 52 l low-voltage detection register 65 m memory, program 25 modulo-n mode t16_out 47 t8_out 43 o oscillator configuration 53 output circuit, counter/timer 49 p package information 20-pin dip package diagram 82 20-pin ssop package diagram 84 28-pin dip package diagram 86 28-pin soic package diagram 85 28-pin ssop package diagram 87 40-pin dip package diagram 87 48-pin ssop package diagram 89 pin configuration 20-pin dip/soic/ssop 5
zgp323h z8 ? otp microcontroller with ir timers ps023803-0305 p r e l i m i n a r y index 98 28-pin dip/soic/ssop 6 40- and 48-pin 8 40-pin dip 7 48-pin ssop 8 pin functions port 0 (p07 - p00) 18 port 0 (p17 - p10) 19 port 0 configuration 19 port 1 configuration 20 port 2 (p27 - p20) 20 port 2 (p37 - p30) 21 port 2 configuration 21 port 3 configuration 22 port 3 counter/timer configuration 24 reset) 25 xtal1 (time-based input 18 xtal2 (time-based output) 18 ping-pong mode 48 port 0 configuration 19 port 0 pin function 18 port 1 configuration 20 port 1 pin function 19 port 2 configuration 21 port 2 pin function 20 port 3 configuration 22 port 3 pin function 21 port 3counter/timer configuration 24 port configuration register 55 power connections 3 power supply 5 program memory 25 map 26 r ratings, absolute maximum 10 register 61 ctr(d)01h 35 ctr0(d)00h 33 ctr2(d)02h 37 ctr3(d)03h 39 flag 80 hi16(d)09h 32 hi8(d)0bh 32 interrupt priority 78 interrupt request 79 interruptmask 79 l016(d)08h 32 l08(d)0ah 32 lvd(d)0ch 65 pointer 80 port 0 and 1 77 port 2 configuration 75 port 3 mode 76 port configuration 55, 75 smr2(f)0dh 40 stack pointer high 81 stack pointer low 81 stop mode recovery 57 stop mode recovery 2 61 stop-mode recovery 73 stop-mode recovery 2 74 t16 control 69 t8 and t16 common control functions 67 t8/t16 control 70 tc16h(d)07h 32 tc16l(d)06h 33 tc8 control 66 tc8h(d)05h 33 tc8l(d)04h 33 voltage detection 71 watch-dog timer 75 register description counter/timer2 ls-byte hold 33 counter/timer2 ms-byte hold 32 counter/timer8 control 33 counter/timer8 high hold 33 counter/timer8 low hold 33 ctr2 counter/timer 16 control 37 ctr3 t8/t16 control 39 stop mode recovery2 40 t16_capture_lo 32 t8 and t16 common functions 35 t8_capture_hi 32
zgp323h z8 ? otp microcontroller with ir timers ps023803-0305 p r e l i m i n a r y index 99 t8_capture_lo 32 register file 30 expanded 26 register pointer 29 detail 31 reset pin function 25 resets and wdt 63 s sclk circuit 58 single-pass mode t16_out 47 t8_out 43 stack 31 standard test conditions 10 standby modes 1 stop instruction, counter/timer 54 stop mode recovery 2 register 61 source 59 stop mode recovery 2 61 stop mode recovery register 57 t t16 transmit mode 46 t16_capture_hi 32 t8 transmit mode 40 t8_capture_hi 32 test conditions, standard 10 test load diagram 10 timing diagram, ac 16 transmit mode flowchart 41 v vcc 5 voltage brown-out/standby 64 detection and flags 65 voltage detection register 71 w watch-dog timer mode registerwatch- dog timer mode regis- ter 62 time select 63 x xtal1 5 xtal1 pin function 18 xtal2 5 xtal2 pin function 18

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